1. Field of the Invention
The invention generally relates to signal delay systems which are used to delay a signal for N period lengths and, more specifically, to signal delay systems which employ the use of integrated circuit shift registers yet which require total capacities which do not correspond to binary steps.
2. Description of the Prior Art
The use of shift registers to delay signals is well known. The delay time which can be achieved with a shift register is dependent on the frequency of the timing signal and the specific number of register elements of the shift register being used. Since the frequency of the timing signal is usually specified beforehand in general transmission systems, a set delay time can be realized only by a shift register with a corresponding number of register elements. However, moderately priced shift registers of integrated circuit designs are predominantly offered in shift register element numbers in binary steps (2.sup.n).
From Beecham U.S. Pat. No. 3,851,154, it is known to delay a digital signal by arranging two such shift registers in parallel and input alternate bits of the signal into each register. In order that the delayed signal be properly merged again at the outputs of the shift registers, it is necessary that the registers each have the same number of stages, i.e., S, in which case the signal is delayed by 2S-1 periods of the timing signal. Assuming that registers are only available in binary steps, i.e., S=2.sup.n (n=1, 2, 3, . . . ) the delay of the input signal by an arbitrary time period is not possible by using the methods taught by Beecham.
Other attempts at digital signal delay with the aid of two or more shift registers in parallel are known but none satisfy the objects of the present invention. Other examples of the prior art are Manship U.S. Pat. No. 3,588,707, Haven U.S. Pat. No. 3,675,049, and Knollenberg et al U.S. Pat. No. 3,941,982.
It is an object of this invention to provide a signal delay system that has the advantage of a shift register with a function of an arbitrary number of register elements using commercially available integrated circuits. It is a further object of this invention to provide a signal delay system particularly well suited to the delay of digitalized video signals. It is yet another object of this invention to provide shift registers with length of several thousands of bits such as those which fall in the binary gradation between 2.sup.10 and 2.sup.13.